Three dimensional (3D) integrated circuits (ICs) have the potential to significantly enhance VLSI chip performance, functionality and device packing density. Interconnects delay and signal integrity issues are critical in chip design. In this paper, we extend the idea of redundant via insertion of conventional 2D ICs and propose an approach for vias insertion/placement in 3D ICs to minimize the propagation delay of interconnects with the consideration of signal integrity. The simulation results based on a 65 nm CMOS technology demonstrate that our approach in general can result in a 9% improvement in average delay and a 26% decrease in reflection coefficient. It is also shown that the proposed approach can be more effective for interconnects delay improvement when it is integrated with the buffer insertion in 3D ICs.

Available statistical skew models are too conservative in estimating the expected clock skew of a well-balanced H-tree. New closed form expressions are presented for accurately estimating the expected values and the variances of both the clock skew and the largest clock delay of a well-balanced H-tree. Based on the new model, clock period optimizations of wafer scale H-tree clock network are investigated under both conventional clocking mode and pipelined clocking mode. It is found that when the conventional clocking mode is used, clock period optimization of wafer scale H-tree is reduced to the minimization of expected largest clock delay under both area restriction and power restriction. On the other hand, when the pipelined clocking mode is considered, the optimization is reduced to the minimization of expected clock skew under power restriction. The results obtained in this paper are very useful in the optimization design of wafer scale H-tree clock distribution networks.

Shared-Memory Optical Packet (SMOP) switch architecture is very promising for significantly reducing the amount of required optical memory, which is typically constructed from fiber delay lines (FDLs). The current reservation-based scheduling algorithms for SMOP switches can effectively utilize the FDLs and achieve a low packet loss rate by simply reserving the departure time for each arrival packet. It is notable, however, that such a simple scheduling scheme may introduce a significant packet out of order problem. In this paper, we first identify the two main sources of packet out of order problem in the current reservation-based SMOP switches. We then show that by introducing a "last-timestamp" variable and modifying the corresponding FDLs arrangement as well as the scheduling process in the current reservation-based SMOP switches, it is possible to keep packets in-sequence while still maintaining a similar delay and packet loss performance as the previous design. Finally, we further extend our work to support the variable-length burst switching.

The capacity of general mobile ad hoc networks (MANETs) remains largely unknown up to now, which significantly hinders the development and commercialization of such networks. Available throughput capacity studies of MANETs mainly focus on either the order sense capacity scaling laws, the exact throughput capacity under a specific algorithm, or the exact throughput capacity without a careful consideration of critical wireless interference and transmission range issues. In this paper, we explore the exact throughput capacity for a class of MANETs, where we adopt group-based scheduling to schedule simultaneous link transmissions for interference avoidance and allow the transmission range of each node to be adjusted. We first determine a general throughput capacity upper bound for the concerned MANETs, which holds for any feasible packet delivery algorithm in such networks. We then prove that the upper bound we determined is just the exact throughput capacity for this class of MANETs by showing that for any traffic input rate within the throughput capacity upper bound, there exists a corresponding two-hop relay algorithm to stabilize such networks. A closed-form upper bound for packet delay is further derived under any traffic input rate within the throughput capacity. Finally, based on the network capacity result, we examine the impacts of transmission range and node density upon network capacity.

We focus on non-conflicting construction of an optical multistage feedforward network to emulate the N-to-1 output buffer multiplexer by using switched fiber delay line (SDL). In [1], Y.T. Chen et al. presented a sufficient condition (an upper bound) for the number of delay lines required for such a multiplexer with variable length bursts. In this paper, we first give an improved upper bound. Then we develop a framework to construct an arrival case of bursts which can be used to achieve a necessary condition (a lower bound). These results are further extended to the feedforward construction of N-to-N output buffer switch. Through simulation and performance comparison, we find that the new bounds can significantly decrease the hardware cost for constructing both the feedforward SDL-based multiplexer and output buffer switch while still provide the same performance as that of the old ones.